AM3703CUS datasheet(142/280 Pages) TI

142 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 4-15. DPLL4 Characteristics (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

prelock-L

Relock time

—Phase lock(3) (Low

7.5 +

μs

DPLL in low-power mode:

power bypass)

125*REFCLKs

lowcurrstdby = 1

trelock-F

Relock time

—Frequency lock(3) (Fast

μs

relock bypass)

prelock-F

Relock time

—Phase lock(3) (Fast

μs

relock bypass)

(1) The minimum frequency on CLKOUT is assuming M2 = 1. For M2

> 1, the minimum frequency on this clock will further scale down by

factor of M2.

(2) The maximum frequency on CLKOUT is assuming M2 = 1.

(3) Relock time assumes typical operating conditions, 10

°C maximum temperature drift.

4.3.2

DLL Characteristics

Table 4-16 summarizes the DLL characteristics and assumes testing over recommended operating

conditions.

Table 4-16. DLL Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

vdda_dplls_dll

Supply voltage for DPLLs (MPU and Core) and

1.71

1.8

1.91

DLL

finput

Input clock frequency (1)

120

200

MHz

Either application mode 0 and 1

tlock

Lock time

500

Clocks

trelock

Relock time (Mode transitions through idle

500

IDLE to MODEMAXDELAY

mode)

250

450

Clocks

IDLE to APPLICATION MODE 1

or 0

1.88

3.38

μs

IDLE to APPLICATION MODE

@133 MHz

1.50

2.71

μs

IDLE to APPLICATION MODE

@166 MHz

1.25

2.25

μs

IDLE to APPLICATION MODE

@200 MHz

(1) Maximum frequency for nominal conditions.

142

Clock Specifications

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