전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AS5013 데이터시트(PDF) 22 Page - ams AG

부품명 AS5013
상세설명  Low Power Integrated Hall IC for Human Interface Applications
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AMSCO [ams AG]
홈페이지  http://www.ams.com
Logo AMSCO - ams AG

AS5013 데이터시트(HTML) 22 Page - ams AG

Back Button AS5013 Datasheet HTML 18Page - ams AG AS5013 Datasheet HTML 19Page - ams AG AS5013 Datasheet HTML 20Page - ams AG AS5013 Datasheet HTML 21Page - ams AG AS5013 Datasheet HTML 22Page - ams AG AS5013 Datasheet HTML 23Page - ams AG AS5013 Datasheet HTML 24Page - ams AG AS5013 Datasheet HTML 25Page - ams AG AS5013 Datasheet HTML 26Page - ams AG Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 32 page
background image
www.ams.com/AS5013
Revision 1.11
22 - 32
AS5013
Datasheet - I² C Registers
8.11 Control Register 2 (2Eh)
Figure 17. Magnet Configuration
Note:
In order to know the polarity of the magnet without any testing device, please refer to Registers Initialization on page 24.
8.12 Hall Element Direct Read Registers (16h to 29h)
Each hall element C1..C5 can be read independently, after each interrupt (data ready).
One hall element value consists of two 12-bit signed-registers: Cx_neg and Cx_pos. For each conversion cycle (i.e. after a readout or Y_res in
idle mode, or at each time-based conversion cycle in Low Power mode), each hall element is read twice: With normal spin (result Cx_pos) and
then with inverted spin (result Cx_neg) in order to remove any hall voltage offset from the hall elements.
The formula to read any hall element Cx:
Cx = (Cx_pos – Cx_neg) / 2
(EQ 1)
Where:
Cx_pos = (Cx_pos[11:8] << 8) | Cx_pos[7:0]
Cx_neg = (Cx_neg[11:8] << 8) | Cx_neg[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Test
Test
Test
ext_clk_en
use_static_offset EN_offset_comp
inv_spinning
pptrim_en
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value: 1000 0100
Bit
Bit Description
7
Test bit. Must configured ‘1’.
6:4
Test bit. Must configured ‘000’.
3
Test bit. Must configured ‘0’.
2
Test bit. Must configured ‘1’.
1
Magnet Polarity bit. Must be set after power up, depending on how the magnet is placed (see Figure 17).
0
Test bit. Must configured ‘0’.
S
N
S
N
S
N
S
N
Magnet configuration 2
Bit Inv_spinning = 0 (default)
AS5013
AS5013
AS5013
AS5013
Magnet configuration 1
Bit Inv_spinning = 1
Magnet configuration 3
Magnet configuration 4
(e.g. EasyPoint modules)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com