AD9142BCPZ datasheet(2/65 Pages) AD

2 / 65 page

AD9142

Data Sheet

Rev. 0 | Page 2 of 64

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

DAC Latency Specifications........................................................ 7

Latency Variation Specifications ................................................ 7

AC Specifications.......................................................................... 7

Operating Speed Specifications.................................................. 8

Absolute Maximum Ratings ....................................................... 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

Serial Port Operation ..................................................................... 18

Data Format ................................................................................ 18

Serial Port Pin Descriptions...................................................... 18

Serial Port Options..................................................................... 18

Data Interface.................................................................................. 20

LVDS Input Data Ports .............................................................. 20

Word Interface Mode................................................................. 20

Byte Interface Mode ................................................................... 20

Data Interface Configuration Options .................................... 20

Interface Delay Line ................................................................... 22

FIFO Operation .............................................................................. 23

Resetting the FIFO ..................................................................... 24

Serial Port Initiated FIFO Reset ............................................... 24

Frame Initiated FIFO Reset....................................................... 24

Digital Datapath.............................................................................. 26

Interpolation Filters ................................................................... 26

Digital Modulation..................................................................... 28

Datapath Configuration ............................................................ 29

Digital Quadrature Gain and Phase Adjustment................... 29

DC Offset Adjustment............................................................... 29

Inverse Sinc Filter....................................................................... 30

Input Signal Power Detection and Protection........................ 30

Transmit Enable Function......................................................... 31

Digital Function Configuration ............................................... 31

Multidevice Synchronization and Fixed Latency....................... 32

Very Small Inherent Latency Variation................................... 32

Further Reducing the Latency Variation................................. 32

Synchronization Implementation ............................................ 33

Synchronization Procedures..................................................... 33

Interrupt Request Operation ........................................................ 34

Interrupt Working Mechanism ................................................ 34

Interrupt Service Routine.......................................................... 34

Temperature Sensor ....................................................................... 35

DAC Input Clock Configurations ................................................ 36

Driving the DACCLK and REFCLK Inputs ........................... 36

Direct Clocking .......................................................................... 36

Clock Multiplication .................................................................. 36

PLL Settings ................................................................................ 37

Configuring the VCO Tuning Band ........................................ 37

Automatic VCO Band Select .................................................... 37

Manual VCO Band Select ......................................................... 37

Analog Outputs............................................................................... 38

Transmit DAC Operation.......................................................... 38

Interfacing to Modulators ......................................................... 39

Reducing LO Leakage and Unwanted Sidebands .................. 40

Example Start-Up Routine ............................................................ 41

Device Configuration Register Map and Description............... 42

SPI Configure Register .............................................................. 44

Power-Down Control Register................................................. 44

Interrupt Enable0 Register........................................................ 44

Interrupt Enable1 Register........................................................ 44

Interrupt Flag0 Register............................................................. 45

Interrupt Flag1 Register............................................................. 45

Interrupt Select0 Register.......................................................... 45

Interrupt Select1 Register.......................................................... 46

DAC Clock Receiver Control Register .................................... 46

Ref Clock Receiver Control Register ....................................... 46

PLL Control Register ................................................................. 47

PLL Status Register..................................................................... 48

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