ISP1507CBS datasheet(21/74 Pages) NXP

21 / 74 page

ISP1507C_ISP1507D_1

Product data sheet

Rev. 01 — 28 May 2008

21 of 74

NXP Semiconductors

ISP1507C; ISP1507D

ULPI HS USB host and peripheral transceiver

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

9.3.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the

ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog

circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;

otherwise undeﬁned behavior may result. When RESET_N is deasserted (HIGH), the DIR

output will deassert (LOW) four or ﬁve clock cycles later. Figure 5 shows the ULPI

behavior when RESET_N is asserted (LOW), and subsequently deasserted (HIGH). If

RESET_N is not used, it must be connected to VCC(I/O).

9.4 VBUS power and fault detection

9.4.1 Driving 5 V on VBUS

The ISP1507 supports external 5 V supplies. The ISP1507 can control the external supply

using the active-LOW PSW_N open-drain output pin. To enable the external supply by

driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG_CTRL

DRV_VBUS bit can be set to any value and will be ignored.

9.4.2 Fault detection

The ISP1507 supports external VBUS fault detector circuits. An overcurrent detection

circuit is required for host applications that supply more than 100 mA on VBUS for voltages

between 4.75 V to 5.25 V. For low-power applications supplying less than 100 mA, the

VBUS power line can directly be connected to the VBUS/FAULT pin on the ISP1507 and the

link can utilize the internal A_VBUS_VLD comparator.

The ISP1507 supports external VBUS fault detector circuits that output a digital fault

indicator signal. The indicator signal must be connected to the VBUS/FAULT pin. To enable

the ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND

bit in the OTG_CTRL register (see Section 10.1.4) and the IND_PASSTHRU bit in the

INTF_CTRL register (see Section 10.1.3) to logic 1. For details, see Figure 7.

Fig 5.

Interface behavior with respect to RESET_N

CLOCK

004aaa720

STP

RESET_N

DATA[7:0]

DIR

NXT

Hi-Z (input)

Hi-Z (link must drive)

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