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AFE4300PNR 데이터시트(PDF) 6 Page - Texas Instruments

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부품명 AFE4300PNR
상세설명  Low-Cost, Integrated Analog Front-End for Weight-Scale and Body Composition Measurement
PDF  30 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

AFE4300PNR 데이터시트(HTML) 6 Page - Texas Instruments

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SCLK
STE
SDIN
SDOUT
t
SCLK
t
CSSC
t
SPWH
t
DIHD
t
SPWL
t
CSDOZ
t
DOHD
t
DOPD
t
SCCS
t
SCSC
t
CSH
t
CSDOD
t
DIST
Hi-Z
Hi-Z
AFE4300
SBAS586B – JUNE 2012 – REVISED JUNE 2013
www.ti.com
SPI TIMING CHARACTERISTICS
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At TA = 0°C to +70°C and VDD = 2 V to 3.6 V, unless otherwise noted.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
tCSSC
STE low to first SCLK setup time(1)
100
ns
tSCLK
SCLK period
250
ns
tSPWH
SCLK pulse width high
100
ns
tSPWL
SCLK pulse width low
100
ns
tDIST
Valid SDIN to SCLK falling edge setup time
50
ns
tDIHD
Valid SDIN to SCLK falling edge hold time
50
ns
tDOPD
SCLK rising edge to valid new SDOUT propagation delay(2)
50
ns
tDOHD
SCLK rising edge to DOUT invalid hold time
0
ns
tCSDOD
STE low to SDOUT driven propagation delay
100
ns
tCSDOZ
STE high to SDOUT Hi-Z propagation delay
100
ns
tCSH
STE high pulse
200
ns
tSCCS
Final SCLK falling edge to STE high
100
ns
(1)
STE can be tied low.
(2)
DOUT load = 20 pF || 100 k
Ω to DGND.
6
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: AFE4300



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