MPC8548ECPXATJB datasheet(68/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

— The input amplitude of the differential clock must be between 400 and 1600 mV differential

peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of

the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.

This requirement is the same for both external DC- or AC-coupled connection.

— For external DC-coupled connection, as described in Section 16.2.1, “SerDes Reference Clock

Receiver Characteristics,” the maximum average current requirements sets the requirement for

average voltage (common mode voltage) to be between 100 and 400 mV. Figure 40 shows the

SerDes reference clock input requirement for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (SGND_SRDSn). Figure 41 shows the SerDes reference clock

input requirement for AC-coupled connection scheme.

•

Single-ended mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400 and 800 mV peak-to-peak (from Vmin to Vmax) with

SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC-

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

SD_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

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