MPC8548ECPXATHC datasheet(130/151 Pages) FREESCALE

130 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

130

Freescale Semiconductor

Clocking

20 Clocking

This section describes the PLL configuration of the device. Note that the platform clock is identical to the

core complex bus (CCB) clock.

20.1

Clock Ranges

Table 75 through Table 77 provide the clocking specifications for the processor cores and Table 78,

through Table 80 provide the clocking specifications for the memory bus.

Table 75. Processor Core Clocking Specifications (MPC8548E and MPC8547E)

Characteristic

Maximum Processor Core Frequency

Unit

Notes

1000 MHz

1200 MHz

1333 MHz

Min

Max

Min

Max

Min

Max

e500 core processor frequency

800

1000

800

1200

800

1333

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. See Section 20.2, “CCB/SYSCLK PLL Ratio,” and Section 20.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

Table 76. Processor Core Clocking Specifications (MPC8545E)

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800 MHz

1000 MHz

1200 MHz

Min

Max

Min

Max

Min

Max

e500 core processor frequency

800

1000

800

1200

MHz

1, 2

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. See Section 20.2, “CCB/SYSCLK PLL Ratio,” and Section 20.3, “e500 Core PLL Ratio,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.

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