Mode

Max Baud

Rate

Minimum

Bit Time

Minimum SCL

Low

Minimum SCL

High

Min Data Set-

up Time

Min/Max Data Hold

Time

Standard

100 KHz

10 μs

4.7 μs

4 μs

250 ns

0 μs/3.45 μs1

Fast

400 KHz

2.5 μs

1.3 μs

0.6 μs

100 ns

0 μs/0.9 μs1

Fast +

1 MHz

1 μs

500 ns

260 ns

50 ns

0 μs/0.45 μs1

High-speed

supported

2.0 MHz

0.5 μs

200 ns

200 ns

10 ns

0 ns/70 ns (100 pf)2

standard.

2. Timing met with IFE = 0, DS = 1, and SE = 1. For more information, refer to Port Control Registers in the

FXLC95000CL Hardware Reference Manual.

spent in low-speed mode.

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Min

Max

Min

Max

SCL clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition. After

this period, the first clock pulse is generated.

4.0

—

0.6

—

μs

LOW period of the SCL clock

4.7

—

1.3

—

μs

HIGH period of the SCL clock

4.0

—

0.6

—

μs

Set-up time for a repeated START condition

4.7

—

0.6

—

μs

01

3.452

01

0.92

μs

Data set-up time

250

—

1003, 4

—

ns

Set-up time for STOP condition

4.0

—

0.6

—

μs

Bus free time between STOP and START

condition

4.7

—

1.3

—

μs

Pulse width of spikes that must be suppressed

by the input filter

N/A

N/A

0

50

μs

acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL

lines.

Mechanical and Electrical Specifications

Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.

29

Freescale Semiconductor, Inc.