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FXLC95000CL 데이터시트(PDF) 10 Page - Freescale Semiconductor, Inc

부품명 FXLC95000CL
상세설명  Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform
PDF  38 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

FXLC95000CL 데이터시트(HTML) 10 Page - Freescale Semiconductor, Inc

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Analog power and ground. VDDA is nominally 1.8V for this device. It is recommended
that this supply voltage be filtered to remove any digital noise that may be present on
the supply.
RESETB
The RESETB pin is an open-drain, bidirectional pin. At power up, it is configured
strictly as an input pin. Setting RCSR[DR] (Reset Control & Status Register “Drive
Reset” bit) to one will cause the RESET function to become bidirectional. Using this
feature, FXLC95000CL can reset external devices whenever it is reset for any purpose
other than power-on-reset.
Slave I2C: SDA0, SCL0
Slave I2C data and clock signals. FXLC95000CL may be controlled via this serial port
or via the slave SPI interface. At reset, SDA0 and SCL0 are open-drain, bidirectional in
input mode, with the pullup resistor disabled.
Master I2C: SDA1, SCL1
Master I2C data and clock signals. Because the FXLC95000CL contains a 32-bit
ColdFire V1 CPU, it is fully capable of mastering other devices in the system via this
serial port.
State at reset: active. SCL1 and SDA1 are configured on pins 1 and 2, respectively. The
alternate functionality on these pins is RGPIO14 and RGPIO15.
Analog-to-Digital Conversion: AN0, AN1
The on-chip ADC can be used to perform a differential analog-to-digital conversion
based upon the voltage present across pins AN0(-) and AN1(+). Conversions for these
pins are at the same Sample Data Rate (SDR) as the MEMS transducer signals.
State at reset: Inactive. AN[1:0] are secondary functions on RGPIO[7:6], which own the
pins at reset.
Rapid General Purpose I/O: RGPIO[15:0]
The ColdFire V1 CPU has a feature called “Rapid GPIO” or RGPIO. This is a 16-bit
input/output port with single-cycle write, set, clear, and toggle functions available to the
CPU. The FXLC95000CL brings out all 16 bits of that port as pins of the device.
State at reset:
• RGPIO[15:14]: inactive. SDA1 and SCL1 own the pin at reset.
General Description
10
Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.
Freescale Semiconductor, Inc.



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