APW7063 datasheet(13/22 Pages) ANPEC

13 / 22 page

Rev. A.10 - Aug., 2009

APW7063

www.anpec.com.tw

Function Pin Description (Cont.)

COMP (Pin 5) (Cont.)

Pull this pin below 0.4V will shutdown the controller, forc-

ing the UGATE and LGATE signals to be 0V. A soft-start

cycle will be initiated upon the release of this pin.

GND (Pin 6)

Signal ground for the IC.

PHASE (Pin 7)

A resistor (R

OCSET) is connected between this pin and the

drain of the low-side MOSFET will determine the over

current limit. An internal 250

µA current source will flow

through this resistor, creating a voltage drop. This volt-

age will be compared with the voltage across the low-

side MOSFET. The threshold of the over current limit is

therefore given by :

250uA

DS(ON)

LIMIT

OCSET

An over current condition will cycle the soft-start function

until the over current condition is removed. Because of

the comparator delay time, the on time of the low-side

MOSFET must be longer than 800ns to have the over

current protection work.

UGATE (Pin 8)

This pin provides gate drive for the high-side MOSFET.

BOOT (Pin 9)

This pin provides the supply voltage to the high side

MOSFET driver. For driving logic level N-channel MOSEFT,

a bootstrap circuit can be used to create a suitable driver’s

supply.

PGND (Pin 10)

Power ground for the gate diver. Connect the lower

MOSFET source to this pin.

LGATE (Pin 11)

This pin provides the gate drive signal for the low side

MOSFET.

VCC (Pin 12)

This pin provides a supply voltage for the device. When

VCC is above the rising threshold 4.2V, it turns on the

device is turned on. Conversely, when VCC is below the

falling threshold 3.9V, the device is turned off.

A 1

µF decoupling capacitor to GND is recommended.

DRIVE (Pin 13)

Connect this pin to the gate of an external N-channel

MOSFET transistor. This pin provides the gate voltage for

the linear regulator pass transistor. It also provides a

means of compensating the linear controller for applica-

tions where the user needs to optimize the regulator tran-

sient response.

FBL (Pin 14)

Connect this pin to the output of the linear regulator via a

proper sized resistor divider. The voltage at this pin is

regulated to 0.8V and the output voltage is determined

using the following equation :











 +

GND

OUT

0.8V

where R

OUT is the resistor connected from VOUT to FBL,

and R

GND is the resistor connected from FBL to GND.

This pin also monitores the under-voltage events. If the

linear regulator is not used, tie the FBL to VREG.

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