PIC16F1508TESSQTO datasheet(81/384 Pages) MICROCHIP

81 / 384 page

 2011 Microchip Technology Inc.

Preliminary

DS41609A-page 81

PIC16(L)F1508/9

7.6.4

PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as

shown in Register 7-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0

R/W-0/0

—

CLC4IE

CLC3IE

CLC2IE

CLC1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-4

Unimplemented: Read as ‘0’

bit 3

CLC4IE: Configurable Logic Block 4 Interrupt Enable bit

1 = Enables the CLC 4 interrupt

0 = Disables the CLC 4 interrupt

bit 2

CLC3IE: Configurable Logic Block 3 Interrupt Enable bit

1 = Enables the CLC 3 interrupt

0 = Disables the CLC 3 interrupt

bit 1

CLC2IE: Configurable Logic Block 2 Interrupt Enable bit

1 = Enables the CLC 2 interrupt

0 = Disables the CLC 2 interrupt

bit 0

CLC1IE: Configurable Logic Block 1 Interrupt Enable bit

1 = Enables the CLC 1 interrupt

0 = Disables the CLC 1 interrupt

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