PIC16F1508TESSQTO datasheet(187/384 Pages) MICROCHIP

187 / 384 page

 2011 Microchip Technology Inc.

Preliminary

DS41609A-page 187

PIC16(L)F1508/9

FIGURE 21-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

21.2.1

SPI MODE REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPxSTAT)

• MSSP Control Register 1 (SSPxCON1)

• MSSP Control Register 3 (SSPxCON3)

• MSSP Data Buffer register (SSPxBUF)

• MSSP Address register (SSPxADD)

• MSSP Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and

STATUS registers in SPI mode operation. The

SSPxCON1 register is readable and writable. The

lower 6 bits of the SSPxSTAT are read-only. The

upper two bits of the SSPxSTAT are read/write.

In SPI master mode, SSPxADD can be loaded with a

value used in the Baud Rate Generator. More informa-

tion on the Baud Rate Generator is available in

Section 21.7 “Baud Rate Generator”

SSPxSR is the shift register used for shifting data in

and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPxSR and SSPxBUF

together create a buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A

write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

SPI Master

SCKx

SDOx

SDIx

General I/O

SCKx

SDIx

SDOx

SSx

SPI Slave

SCKx

SDIx

SDOx

SSx

SPI Slave

SCKx

SDIx

SDOx

SSx

SPI Slave

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