| 전자부품 데이터시트 검색엔진 |
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8902A 데이터시트(PDF) 4 Page - Allegro MicroSystems |
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8902A 데이터시트(HTML) 4 Page - Allegro MicroSystems |
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4 / 12 page ![]() 8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 SERIAL PORT TIMING CONDITIONS Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units CWD Current ICWD Charging -9.0 -10 -11 µA CWD Threshold Voltage VTL 0.22 0.25 0.28 V VTH 2.25 2.5 2.75 V Max. FLL Oscillator Frequency fOSC VDD = 5.0 V, TA = 25 °C12 —— MHz IOUT(MAX) — D3 = 0, D4 = 0 1.0 1.2 1.4 A D3 = 0, D4 = 1 0.9 1.0 1.1 A D3 = 1, D4 = 0 0.5 0.6 0.7 A D3 = 1, D4 = 1 — 250 — mA BRAKE Threshold VBRK 1.5 1.75 2.0 V BRAKE Hysteresis Current IBRKL VBRK = 750 mV — 20 — µA Transconductance Gain gm 0.42 0.50 0.58 A/V Centertap Resistors RCT 5.0 10 13 k Ω Back-EMF Hysteresis — VBEMF - VCTAP at 5.0 20 37 mV FCOM Transition -5.0 -20 -37 mV ELECTRICAL CHARACTERISTICS continued DATA CLOCK Dwg. WP-019 A C B D C D CHIP SELECT E A. Minimum CHIP SELECT setup time before CLOCK rising edge .......... 100 ns B. Minimum CHIP SELECT hold time after CLOCK rising edge ............... 150 ns C. Minimum DATA setup time before CLOCK rising edge ........................ 150 ns D. Minimum DATA hold time after CLOCK rising edge ............................. 150 ns E. Minimum CLOCK low time before CHIP SELECT .................................. 50 ns F. Maximum CLOCK frequency .............................................................. 3.3 MHz |
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