AD7225LP datasheet(20/24 Pages) AD

20 / 24 page

AD7225

Rev. C | Page 20 of 24

VSS GENERATION

Operating the AD7225 from dual supplies results in enhanced

performance over single-supply operation on a number of

parameters as previously outlined. Some applications may

require this enhanced performance, but may only have a single

power supply rail available. The circuit of Figure 29 shows a

method of generating a negative voltage using one CD4049,

operated from a VDD of 15 V. Two inverters of the hex inverter

chip are used as an oscillator. The other four inverters are in

parallel and used as buffers for higher output current. The

square wave output is level translated to a negative-going signal,

then rectified and filtered. The circuit configuration shown

provides an output voltage of −5.1 V for current loadings in the

range of 0.5 mA to 9 mA. This satisfies the AD7225 ISS require-

ment over the commercial operating temperature range.

1/6

CD4049AE

1/6

CD4049AE

1/6

CD4049AE

1/6

CD4049AE

1/6

CD4049AE

1/6

CD4049AE

510k

Ω

5.1k

Ω

0.02µF

47µF

5V1

–VOUT

1N4001

510

Ω

Figure 29. VSS Generation Circuit

AD7225LP 데이터시트(PDF) 20 Page - Analog Devices