A3P030 datasheet(83/220 Pages) MICROSEMI

83 / 220 page

ProASIC3 Flash Family FPGAs

Revision 13

2-69

Table 2-96 • Parameter Definition and Measuring Nodes

Parameter Name

Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ

Clock-to-Q of the Output Data Register

H, DOUT

tOSUD

Data Setup Time for the Output Data Register

F, H

tOHD

Data Hold Time for the Output Data Register

F, H

tOSUE

Enable Setup Time for the Output Data Register

G, H

tOHE

Enable Hold Time for the Output Data Register

G, H

tOPRE2Q

Asynchronous Preset-to-Q of the Output Data Register

L, DOUT

tOREMPRE

Asynchronous Preset Removal Time for the Output Data Register

L, H

tORECPRE

Asynchronous Preset Recovery Time for the Output Data Register

L, H

tOECLKQ

Clock-to-Q of the Output Enable Register

H, EOUT

tOESUD

Data Setup Time for the Output Enable Register

J, H

tOEHD

Data Hold Time for the Output Enable Register

J, H

tOESUE

Enable Setup Time for the Output Enable Register

K, H

tOEHE

Enable Hold Time for the Output Enable Register

K, H

tOEPRE2Q

Asynchronous Preset-to-Q of the Output Enable Register

I, EOUT

tOEREMPRE

Asynchronous Preset Removal Time for the Output Enable Register

I, H

tOERECPRE

Asynchronous Preset Recovery Time for the Output Enable Register

I, H

tICLKQ

Clock-to-Q of the Input Data Register

A, E

tISUD

Data Setup Time for the Input Data Register

C, A

tIHD

Data Hold Time for the Input Data Register

C, A

tISUE

Enable Setup Time for the Input Data Register

B, A

tIHE

Enable Hold Time for the Input Data Register

B, A

tIPRE2Q

Asynchronous Preset-to-Q of the Input Data Register

D, E

tIREMPRE

Asynchronous Preset Removal Time for the Input Data Register

D, A

tIRECPRE

Asynchronous Preset Recovery Time for the Input Data Register

D, A

Note: *See Figure 2-14 on page 2-68 for more information.

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