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AM28F010 데이터시트(PDF) 27 Page - Advanced Micro Devices

부품명 AM28F010
상세설명  1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
PDF  35 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM28F010 데이터시트(HTML) 27 Page - Advanced Micro Devices

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Am28F010
27
AC CHARACTERISTICS—Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
4. Not 100% tested.
Parameter Symbols
Am28F010 Speed Options
JEDEC
Standard
Description
-70
-90
-120
-150
-200
Unit
tAVAV
tWC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
tAVWL
tAS
Address Setup Time
Min
0
0
0
0
0
ns
tWLAX
tAH
Address Hold Time
Min
45
45
506075
ns
tDVWH
tDS
Data Setup Time
Min
45
45
50
50
50
ns
tWHDX
tDH
Data Hold Time
Min
10
10
10
10
10
ns
tWHGL
tWR
Write Recovery Time Before Read
Min
6
6
6
6
6
µs
tGHWL
Read Recovery TIme Before Write
Min
0
0
0
0
0
µs
tELWL
tCS
CE
# Setup TIme
Min0
0
0
0
0ns
tWHEH
tCH
CE
# Hold TIme
Min
0
0
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min
45
45
50
60
60
ns
tWHWL
tWPH
Write Pulse Width High
Min
20
20
20
20
20
ns
tWHWH1
Duration of Programming Operation
(Note 2)
Min
10
10
101010
µs
tWHWH2
Duration of Erase Operation (Note 2)
Min
9.5
9.5
9.5
9.5
9.5
ms
tVPEL
VPP Setup Time to Chip Enable Low (Note 4)
Min
100
100
100
100
100
ns
tVCS
VCC Setup Time to Chip Enable Low (Note 4)
Min
50
50
50
50
50
µs
tVPPR
VPP Rise Time (Note 4) 90% VPPH
Min
500
500
500
500
500
ns
tVPPF
VPP Fall Time (Note 4) 10% VPPL
Min
500
500
500
500
500
ns
tLKO
VCC < VLKO to Reset (Note 4)
Min
100
100
100
100
100
ns



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