AM7968 datasheet(96/127 Pages) AMD

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AMD

TAXIchip Integrated Circuit Technical Manual

For example, consider transmitting Hex

B [1011], encoded as 10111. Error E occurs

changes bits b0 & b1, resulting in encoded pattern 10100, which is Hex 2 [0010]

2 bits changed, and the run length the error = 4 bits,

1 0 1 1

0 0 1 0

becomes

2 bits changed, and the run length

the error = 4 bits,

A double bit error can change valid data into a Violation, a valid Command byte, a 1-bit,

2-bit, 3-bit,or 4-bit data error. A summary of the occurrence of these errors for the six

error locations for 4B/5B encoding is summarized below in Table B1.

Table B-1

Error Type

ABCD

V=5

V=3

V=1

C=5

C=3

C=5

C=3

C=5

C=1

1B=4

1B=0

1B=2

1B=4

1B=0

1B=14

2B=2

2B=8

2B=4

2B=6

2B=0

3B=0

4B=0

4B=2

4B=0

Table B-2

Similar reasoning for the 5B/6B encoding scheme results in seven possible error

locations, and the summary of the occurrence of these errors is listed below:

ABCD

V=13

V=16

V=12

V=6

V=9

V=10

V=5

C=3

C=2

C=4

C=3

C=4

C=3

1B=10

1B=0

1B=8

1B=2

1B=22

2B=6

2B=14

2B=12

2B=14

2B=12

2B=2

3B=0

3B=4

3B=6

3B=0

4B=0

4B=2

4B=0

4B=4

4B=0

Utilizing this information one can determine the efficiency of the violation logic in the

TAXI Receiver. Figure B2 summarizes the violation effectiveness, as well as depicting

the number of bits in error in the undetected corrupted data. This information can be

extremely useful in determining what, if any, additional error detection schemes should

be implemented. Figure B3 graphically represents the run length of the corrupted data

for the undetected errors. As shown in this figure, there are a small percentage of

unlimited run length errors. This is due to the few data patterns, which, when corrupted

will cause a false Sync pattern to be generated. This pattern will cause a running error

which will continue until the next valid Sync realigns the byte edge to its proper position.

While these

false Syncs occur very rarely, these are the most dangerous errors in a

TAXI system, this very well may dictate the maximum user

packet size.

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