AMD

24

Am7992B

SWITCHING WAVEFORMS

03378I-22

2.0 V

0.8 V

2.0

0.8

2.0

0.8

0.8 V

0.8 V

0.8 V

2.0 V

25

24

26

27

28

29

28

TCLK

TX

TENA

TCLK and TX Timing

0.8

2.0

1.5

1.5

1.5

1.5

X1

Driving

Input

TCLK

Transmit+, Transmit–

(Note A)

0.8

2.0

35

34

‘A’

‘B’

0 V

BCC

(Bit Cell Center)

BCB

(Bit Cell Boundary)

03378I-23

Note:

A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’.

*See Specification for External TTL Level in Functional Description section.

X1 Driven from External Source