AM7968-125JC datasheet(58/127 Pages) AMD

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AMD

TAXIchip Integrated Circuits Technical Manual

The TAXIchip set uses 4B/5B or 5B/6B coding, so that

m is either 4 or 5, and n is either

5 or 6. In 8-bit mode, each 4-bit nibble is presented to one of two 4B/5B encoders to

produce 10 code bits, 5 from each encoder. In 9-bit mode, the more significant 4B/5B

encoder is replaced with a 5B/6B encoder to yield a total of 11 code bits. In 10-bit mode,

both encoders are replaced with 5B/6B encoders, yielding a total of 12 code bits.

The TAXIchip set can encode two types of data: either 8, 9, or 10-bit Data, or Com-

mands. Commands are special symbols which are typically used as control functions at

the receiving end of the link. Commands may be four, three, or two bits wide, corre-

sponding to a Data width of eight, nine, or ten bits respectively. The presence of any

non-ZERO bits on the Command inputs when STRB is asserted will cause a Command

symbol to be sent, regardless of the state of the Data lines. The Command bits are

encoded into 10,11, or 12 bit groupings which are special cases of the 4B/5B or 5B/6B

code not used for Data.

In the absence of Data or Commands, a unique symbol (Sync) is automatically gener-

ated to maintain link synchronization. If the user has not supplied a STRB during a byte,

a Sync symbol is sent.

NRZI stands for Non-Return to Zero, Invert on one. Logic ONEs are indicated by a

transition, while logic ZEROs produce no transition. Further encoding the 4B/5B

encoded data in this way ensures that the Receiver PLL will get a transition at least

every three clock times (the maximum number of ZEROs in the 4B/5B code). Since a

PLL can make a phase comparison and initiate a correction only at a transition,

maximizing the number of transitions helps to keep the loop solidly in lock.

AM7968-125JC 데이터시트(PDF) 58 Page - Advanced Micro Devices