AM79C940VCW datasheet(19/122 Pages) AMD

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AMD

Am79C940

PIN DESCRIPTION

Network Interfaces

The MACE device has five potential network interfaces.

Only one of the interfaces that provides physical net-

work attachment can be used (active) at any time. Se-

lection between the AUI, 10BASE-T, DAI or GPSI ports

is provided by programming the PHY Configuration

Control register. The EADI port is effectively active at all

times. Some signals, primarily used for status reporting,

are active for more than one single interface (the CLSN

pin for instance). Under each of the descriptions for the

network interfaces, the primary signals which are

unique to that interface are described. Where signals

are active for multiple interfaces, they are described

once under the interface most appropriate.

Attachment Unit Interface (AUI)

CI+/CI

Control In

(Input)

A differential input pair, signalling the MACE device that

a collision has been detected on the network media, in-

dicated by the CI

± inputs being exercised with 10 MHz

pattern of sufficient amplitude and duration. Operates at

pseudo-ECL levels.

DI+/DI

Data In

(Input)

A differential input pair to the MACE device for receiving

Manchester encoded data from the network. Operates

at pseudo-ECL levels.

DO+/DO

Data Out

(Output)

A differential output pair from the MACE device for

transmitting Manchester encoded data to the network.

Operates at pseudo-ECL levels.

Digital Attachment Interface (DAI)

TXDAT+/TXDAT–

Transmit Data

(Output)

When the DAI port is selected, TXDAT

± are configured

as a complementary pair for Manchester encoded data

output from the MACE device, used to transmit data to a

local external network transceiver. During valid trans-

mission (indicated by

TXEN low), a logical 1 is indicated

by the TXDAT+ pin being in the high state and TXDAT–

in the low state; and a logical

0 is indicated by the

TXDAT+ pin being in the low state and TXDAT– in the

high state. During idle (

TXEN high), TXDAT+ will be in

the high state, and TXDAT– in the low state. When the

GPSI port is selected, TXDAT+ will provide NRZ data

output from the MAC core, and TXDAT– will be held in

the LOW state. Operates at TTL levels. The operations

of TXDAT+ and TXDAT– are defined in the following

tables:

TXDAT+ Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

High Impedance (Note 2)

10BASE-T

High Impedance (Note 2)

DAI Port

TXDAT+ Output

GPSI

TXDAT+ Output

Status Disabled

High Impedance (Note 2)

TXDAT– Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Pin Function

Sleep Mode

High Impedance

AUI

High Impedance

10BASE-T

High Impedance

DAI Port

TXDAT– Output

GPSI

LOW

Status Disabled

High Impedance

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

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