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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM79C940VCW 데이터시트(PDF) 77 Page - Advanced Micro Devices |
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AM79C940VCW 데이터시트(HTML) 77 Page - Advanced Micro Devices |
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77 / 122 page  AMD 77 Am79C940 Programmer’s Register Model (continued) Addr Mnemonic Contents R/W 9 IMR Interrupt Mask Register 80 JABM Jabber Error Mask 40 BABLM Babble Error Mask 20 CERRM Collision Error Mask 10 RCVCCOM Receive Collision Count Overflow Mask 08 RNTPCOM Runt Packet Count Overflow Mask 04 MPCOM Missed Packet Count Overflow Mask 02 RCVINTM Receive Interrupt Mask 01 XMTINTM Transmit Interrupt Mask 10 PR Poll Register 80 XMTSV Transmit Status Valid RO 40 TDTREQ Transmit Data Transfer Request 20 RDTREQ Receive Data Transfer Request 11 BIUCC Bus Interface Unit Configuration Control 80 — 40 BSWP Byte Swap 30 XMTSP—Transmit Start Point (2 bits) 00 Transmit after 4 bytes have been loaded 01 Transmit after 16 bytes have been loaded 10 Transmit after 64 bytes have been loaded 11 Transmit after 112 bytes have been loaded 01 SWRST Software Reset 12 FIFOCC FIFO Configuration Control C0 XMTFW Transmit FIFO Watermark (2 bits) 00 Assert TDTREQ after 8 write cycles can be made 01 Assert TDTREQ after 16 write cycles can be made 10 Assert TDTREQ after 32 write cycles can be made 11 XX 30 RCVFW Receive FIFO Watermark (2 bits) 00 Assert RDTREQ after 16 bytes are present 01 Assert RDTREQ after 32 bytes are present 10 Assert RDTREQ after 64 bytes are present 11 XX 08 XMTFWU Transmit FIFO Watermark Update—loads XMTFW bits 04 RCVFWU Receive FIFO Watermark Update—loads RCVFW bits 02 XMTBRST Select Transmit Burst mode 01 RCVBRST Select Receive Burst mode 13 MACCC Media Access Control (MAC) Configuration Control 80 PROM Promiscuous mode 40 DXMT2PD Disable Transmit Two Part Deferral 20 EMBA Enable Modified Back-off Algorithm 10 — 08 DRCVPA Disable Receive Physical Address 04 DRCVBC Disable Receive Broadcast 02 ENXMT Enable Transmit 01 ENRCV Enable Receive R/W R/W R/W R/W |
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