AM79C978VCSLASHW datasheet(61/261 Pages) AMD

61 / 261 page

Am79C978

Figure 33 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

Note that the value of CSR2, bits 15-8, is used as the

upper 8-bits for all memory addresses during bus mas-

ter transfers.

Figure 34 illustrates when SSIZE32 is set to 1, the re-

lationship between the initialization base address, the

initialization block, the receive and transmit descriptor

ring base addresses, the receive and transmit descrip-

tors, and the receive and transmit data buffers.

Figure 33.

16-Bit Software Model

22206B-36

Initialization

Block

IADR[15:0]

IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE

RES

RDRA[23:16]

TLE

RES

TDRA[23:16]

Rcv

Buffers

RMD

Rcv Descriptor

Ring

•

1st desc.

start

2nd

desc.

RMD0

Xmt

Buffers

TMD

Xmt Descriptor

Ring

•

1st desc.

start

2nd

desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

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