AM79C978VCSLASHW datasheet(137/261 Pages) AMD

137 / 261 page

Am79C978

137

CSR66: Next Transmit Byte Count

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved locations. Read and

written as zeros.

11-0

NXBC

Next Transmit Byte Count. This

field is a copy of the BCNT field of

TMD1 of the next transmit de-

scriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR67: Next Transmit Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

NXST

Next Transmit Status. This field is

a copy of bits 31-16 of TMD1 of

the next transmit descriptor.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

7-0

RES

Reserved locations. Read and

written as zeros. Accessible only

when either the STOP or the

SPND bit is set.

CSR72: Receive Ring Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCVRC

Receive Ring Counter location.

Contains a two’s complement bi-

nary number used to number the

current receive descriptor. This

counter interprets the value in

CSR76 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR74: Transmit Ring Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

XMTRC

Transmit Ring Counter location.

Contains a two’s complement bi-

nary number used to number the

current transmit descriptor. This

counter interprets the value in

CSR78 as pointing to the first de-

scriptor. A counter value of zero

corresponds to the last descriptor

in the ring.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR76: Receive Ring Length

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCVRL

Receive Ring Length. Contains

the two’s complement of the re-

ceive descriptor ring length. This

Am79C978 controller’s initializa-

tion routine based on the value in

the RLEN field of the initialization

block. However, this register can

be manually altered. The actual

receive ring length is defined by

the current value in this register.

The ring length can be defined as

any value from 1 to 65535.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

AM79C978VC/W 데이터시트(PDF) 137 Page - Advanced Micro Devices

AM79C978VC/W 데이터시트(HTML) 137 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL