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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AMD-K6 데이터시트(PDF) 60 Page - Advanced Micro Devices |
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AMD-K6 데이터시트(HTML) 60 Page - Advanced Micro Devices |
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60 / 346 page  42 Software Environment Chapter 3 AMD-K6® Processor Data Sheet 20695H/0—March 1998 Preliminary Information Paging The AMD-K6 processor can address up to 4 Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set up in the Page Directory Entries (PDE) and Page Table Entries (PTE). The processor can access both 4-Kbyte pages and 4-Mbyte pages, and the page sizes can be intermixed within a page directory. When the Page Size Extension (PSE) bit in CR4 is set, the processor translates linear addresses using either the 4-Kbyte Translation Lookaside Buffer (TLB) or the 4-Mbyte TLB, depending on the state of the page size (PS) bit in the page directory entry. Figures 35 and 36 show how 4-Kbyte and 4-Mbyte page translations work. Figure 35. 4-Kbyte Paging Mechanism Linear Address Page Directory Page Table 4-Kbyte Page Frame CR3 0 11 12 21 31 22 Page Directory Offset Page Table Offset Page Offset PDE PTE Physical Address |
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