AMC008DFLKA datasheet(14/46 Pages) AMD

14 / 46 page

AmC0XXDFLKA

Sector erase does not require the user to program the

device prior to erase. The device automatically pro-

grams all memory locations to “0” in the sector(s) to be

erased prior to electrical erase. When erasing a sector

or sectors the remaining unselected sectors are not af-

fected. The system is not required to provide any con-

trols or timings during these operations. A Reset

command after the device has begun execution will

stop the device but the data in the operated sector will

be undeﬁned. In that case, restart the erase on that

sector and allow it to complete.

The automatic sector erase begins after the 50

µs time

out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the

data on D7 is “1” (see Write Operation Status section)

at which time the device returns to read mode. Data

Polling must be performed at an address within any of

the sectors being erased.

Figure 1 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Embedded Program Algorithm

The Embedded Program setup is a four bus cycle op-

eration that stages the addressed memory sector or

memory segment for automatic programming.

Once the Embedded Program setup operation is per-

formed, the next WE pulse causes a transition to an ac-

tive programming operation. Addresses are internally

latched on the falling edge of the WE pulse. Data is in-

ternally latched on the rising edge of the WE pulse. The

rising edge of WE also begins the programming opera-

tion. The system is not required to provide further con-

trol or timing. The device will automatically provide an

adequate internally generated write pulse and verify

margin. The automatic programming operation is com-

pleted when the data on D7 of the addressed memory

sector or memory segment is equivalent to data written

to this bit (see Write Operation Status section) at which

time the device returns to the Read mode (no write ver-

ify command is required).

Addresses are latched on the falling edge of WE during

the Embedded Program command execution and

hence the system is not required to keep the addresses

stable during the entire Programming operation. How-

ever, once the device completes the Embedded Pro-

gram operation, it returns to the Read mode and

addresses are no longer latched. Therefore, the device

requires that a valid address input to the device is sup-

plied by the system at this particular instant of time.

Otherwise, the system will never read a valid data on

D7. A system designer has two choices to implement

the Embedded Programming algorithm:

1. The system (CPU) keeps the address valid during

the entire Embedded Programming operation, or

2. Once the system executes the Embedded Program-

ming command sequence, the CPU takes away the

address from the device and becomes free to do

other tasks. In this case, the CPU is required to

keep track of the valid address by loading it into a

temporary register. When the CPU comes back for

performing Data Polling, it should reassert the same

address.

However, since the Embedded Programming operation

takes only 8

µs typically, it may be easier for the CPU

to keep the address stable during the entire Embedded

Programming operation instead of reasserting the valid

address during Data Polling. Anyway, this has been left

to the system designer’s choice to go for either opera-

tion. Any commands written to the segment during this

period will be ignored.

Figure 2 and Table 7 illustrate the Embedded Program

Algorithm, a typical command string, and bus operation.

Reset Command

The Reset command initializes the sector or segment

to the read mode. Please refer to Tables 3 and 4, “Byte

Command Deﬁnitions,” and Table 5, “Word Command

Deﬁnitions” for the Reset command operation. The

sector or segment remains enabled for reads until the

command register contents are altered.

19521D-2

Figure 1.

Embedded Erase Algorithm

Write Embedded Erase

Command Sequence

(Table 3 and 4)

Data Poll from Device

(Figure 3)

Start

Erasure Complete

Table 7.

Embedded Program Algorithm

Bus Operation

Command

Comments

Standby

Wait for VCC ramp

Write

Embedded Program

command sequence

3 bus cycle

operation

Write

Program Address/

Data

1 bus cycle

operation

Read

Data Polling to

verify program

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