AmMCL00XA

15

PRELIMIN ARY

Table 8.

Memory Sector Addresses

Notes:

1. For word addressing, devices 0 and 1 (S0 and S1) together form Memory Device Pair 0; devices 2 and 3 (S2 and S3) form

Memory Device Pair 1. Refer to the block diagram for device connections.

2. Card address bits range from A0 to A19. Host address bits range from A0 to A20. Host address bit A0 is used for controlling

the CEL# and CEH# inputs to the card. Refer to Figure 2 for host-to-card address bit connections.

Sector

Card Address Bits

Device 0 and/or 1 (Note 1)

Device 2 and/or 3 (Note 1)

A19

A18

A17

A16

Card Address Range

Card Address Range

0

0

0

0

0

00000h–0FFFFh

100000h–10FFFFh

1

0

0

0

1

10000h–1FFFFh

110000h–11FFFFh

2

0

0

1

0

20000h–2FFFFh

120000h–12FFFFh

3

0

0

1

1

30000h–3FFFFh

130000h–13FFFFh

4

0

1

0

0

40000h–4FFFFh

140000h–14FFFFh

5

0

1

0

1

50000h–5FFFFh

150000h–15FFFFh

6

0

1

1

0

60000h–6FFFFh

160000h–16FFFFh

7

0

1

1

1

70000h–7FFFFh

170000h–17FFFFh

8

1

0

0

0

80000h–8FFFFh

180000h–18FFFFh

9

1

0

0

1

90000h–9FFFFh

190000h–19FFFFh

10

1

0

1

0

A0000h–AFFFFh

1A0000h–1AFFFFh

11

1

0

1

1

B0000h–BFFFFh

1B0000h–1BFFFFh

12

1

1

0

0

C0000h–CFFFFh

1C0000h–1CFFFFh

13

1

1

0

1

D0000h–DFFFFh

1D0000h–1DFFFFh

14

1

1

1

0

E0000h–EFFFFh

1E0000h–1EFFFFh

15

1

1

1

1

F0000h–FFFFFh

1F0000h–1FFFFFh