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APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

R

3

R

1a

L

1

L

2

R

1b

C

1a

C

1b

C

A

CP

1

CP

3

VINCM

1V

CP

4

CP

2

INP

INM

All switches OFF Resistance: 10 GW

ADS5522

SBAS320C – MAY 2004 – REVISED FEBRUARY 2007

clock cycle. This process results in a data latency of

17.5 clock cycles, after which the output data is

available as a 12-bit parallel word, coded in either

The ADS5522 is a low-power, 12-Bit, 80 MSPS,

straight offset binary or binary two's complement

CMOS,

switched

capacitor,

pipeline

ADC

that

format.

operates from a single 3.3-V supply. The conversion

process is initiated by a falling edge of the external

input clock. Once the signal is captured by the input

S&H, the input sample is sequentially converted by a

The analog input for the ADS5522 consists of a

series of small resolution stages, with the outputs

differential

sample-and-hold

architecture

combined in a digital correction logic block. Both the

implemented using the switched capacitor technique

rising and the falling clock edges are used to

shown in Figure 37.

propagate the sample through the pipeline every half

NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period.

Figure 37. Analog Input Stage

20

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