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MACH211SP-7VC 데이터시트(PDF) 17 Page - Advanced Micro Devices

부품명 MACH211SP-7VC
상세설명  High-Density EE CMOS Programmable Logic
PDF  37 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

MACH211SP-7VC 데이터시트(HTML) 17 Page - Advanced Micro Devices

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MACH211SP-10/12 (Ind)
17
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
f = 1 MHz
6pF
COUT
Output Capacitance
VOUT = 2.0 V
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-10
-12
Unit
Min
Max
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
10
12
ns
tS
Setup Time from Input, I/O, or Feedback to Clock
D-type
6.5
8
ns
T-type
7.5
9
ns
tH
Register Data Hold Time
0
0
ns
tCO
Clock to Output (Note 3)
6
7.5
ns
tWL
Clock Width
LOW
5
6
ns
tWH
HIGH
5
6
ns
fMAX
Maximum
Frequency
(Note 1)
External Feedback
1/(tS + tCO)
D-type
80
64
MHz
T-type
74
59
MHz
Internal Feedback (fCNT)
D-type
100
80
MHz
T-type
91
72.5
MHz
No Feedback
1/(tWL + tWH)
100
80
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
6.5
8
ns
tHL
Latch Data Hold Time
0
0
ns
tGO
Gate to Output
8
8.5
ns
tGWL
Gate Width LOW
5
6
ns
tPDL
Input, I/O, or Feedback to Output Through Transparent Input or
Output Latch
12
14.5
ns
tSIR
Input Register Setup Time
2
2.5
ns
tHIR
Input Register Hold Time
2
3
ns
tICO
Input Register Clock to Combinatorial Output
13
16
ns
tICS
Input Register Clock to Output Register Setup
D-type
10
12
ns
T-type
11
13
ns
tWICL
Input Register Clock Width
LOW
5
6
ns
tWICH
HIGH
5
6
ns
fMAXIR
Maximum Input Register Frequency
1/(tWICL + tWICH)
100
80
MHz
tSIL
Input Latch Setup Time
2
2.5
ns
tHIL
Input Latch Hold Time
2
3
ns
tIGO
Input Latch Gate to Combinatorial Output
14
17
ns
tIGOL
Input Latch Gate to Output Through Transparent Output Latch
16
19.5
ns



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