Functional description

L9777

14/25

Doc ID 13496 Rev 2

3.4

RESET adjustable threshold

The under voltage threshold value (VCCUN) can be set between 0.7VCC (typ.) and

0.96VCC (typ) by connecting external resistor divider to RADJ pin (see Figure 11). This

feature can be used with microprocessors that guarantee a safe operation with supply

voltage lower than internal reset threshold. The calculation of this threshold is given by:

VCCUN_ext = VRADJTH (1+R1/R2)

(neglecting RADJ input current)

where: VRADJTH=1.2V (typ) and VCCUN_ext is the reset threshold.

If this features is not needed, RADJ pin has to be connected to GND, in this case the

internal under voltage threshold value is 0.94*VCC (typ.).

Figure 11.

Resistor divider to adjust the under voltage threshold

3.5

Watchdog

The watchdog input WD monitors a connected microcontroller. If pulses are missing, the

output NMI is set to low. The minimum WD frequency to avoid reset event can be set with

the external capacitor CD. The watchdog circuit charges and discharges the capacitor CD

with the constant currents IWC and IWD, counting the number of oscillations as for TRD

delay time. If no rising edge is sensed on pin WD between 48 oscillation periods (TWOP -

TWOL, time A to B in Figure 12), a watchdog reset is generated. To prevent this reset the

microcontroller must generate a positive edge during this time window in order to reset the

counter.

Minimum frequency of microprocessor input signal can be calculated using following

equation:

Every WD positive edge resets the counter and makes a synchronization between internal

oscillator and external WD input signal.

Synchronization is realized changing the current from charging to discharging if rising edge

is detected during rising ramp on CD (time D in Figure 12). Otherwise if rising edge is

detected during falling ramp on CD, no current inversion is performed (time E). This

operation leads to a maximum error of half oscillation period on TWOP - TWOL time

window. When NMI goes low for watchdog reset, the counter will go on for other 16 counts,

returning to initial state (time B to C in Figure 12). During this time (TWOL) the NMI remains

low and WD edges are masked, so the TWOL reset time is fully guaranteed.

The Watchdog operation is not active only if WD_EN input pin is set low.

RADJ

VCC

L9777

R1

R2