A43L0616AV datasheet(35/45 Pages) AMICC

35 / 45 page

A43L0616A

(May, 2001, Version 1.0)

AMIC Technology, Inc.

Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Burst Length = Full Page)

High

CLOCK

CKE

RAS

CAS

ADDR

Row Active

(A-Bank)

: Don't care

RAa

A10/AP

CAa

RAa

DQM

DAa4

DAa3

DAa1

DAa2

DAb0

DAb1

DAb2

DAb3

Precharge

(A-Bank)

Write

(A-Bank)

CAb

Write

(A-Bank)

Burst Stop

* Note 1

* Note 2

DAa0

DAb4

DAb5

tRDL

tBDL

* Note 3

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.

It is defined by AC parameter of tBDL(=1CLK).

3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.

It is defined by AC parameter of tRDL(=2CLK).

DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.

DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

4. Burst stop is valid only at every burst length.

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