JS28F640P33TF70 datasheet(38/88 Pages) NUMONYX

38 / 88 page

P33-65nm

Datasheet

Jul 2011

Order Number: 208034-04

11.1.6

Data Output Configuration (RCR.9)

The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word

remains valid on the data bus for one or two clock cycles. This period of time is called

the “data cycle”. When DOC is set, output data is held for two clocks (default). When

DOC is cleared, output data is held for one clock (see Figure 11, “Data Hold Timing” on

page 38). The processor’s data setup time and the flash memory’s clock-to-data output

delay should be considered when determining whether to hold output data for one or

two clocks. A method for determining the Data Hold configuration is shown below:

To set the device at one clock data hold for subsequent reads, the following condition

must be satisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

tDATA = Data set up to Clock (defined by CPU)

For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming

tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:

20 ns + 4 ns ≤ 25 ns

The equation is satisfied and data will be available at every clock period with data hold

setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of

2 clock periods must be used.

Table 15: WAIT Functionality Table

Condition

WAIT

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

High-Z

CE# =’0’, OE# = ‘0’

Active

Synchronous Array Reads

Active

Synchronous Non-Array Reads

Active

All Asynchronous Reads

Deasserted

All Writes

High-Z

1,2

Notes:

Active: WAIT is asserted until data becomes valid, then deasserts.

When OE# = VIH during writes, WAIT = High-Z.

Figure 11: Data Hold Timing

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

CLK [C]

D[15:0] [Q]

2 CLK

Data Hold

1 CLK

Data Hold

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