| 전자부품 데이터시트 검색엔진 |
|
STM32F103RG 데이터시트(PDF) 72 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F103RG 데이터시트(HTML) 72 Page - STMicroelectronics |
|
72 / 120 page ![]() Electrical characteristics STM32F103xF, STM32F103xG 72/120 Doc ID 16554 Rev 3 Figure 29. Synchronous non-multiplexed PSRAM write timings Table 39. Synchronous non-multiplexed PSRAM write timings(1) 1. CL = 15 pF. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 27.6 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1.5 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 1.5 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1.5 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 2.5 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |