STM32F103RG datasheet(89/120 Pages) STMICROELECTRONICS

89 / 120 page

STM32F103xF, STM32F103xG

Electrical characteristics

Doc ID 16554 Rev 3

89/120

Figure 44.

I/O AC characteristics definition

5.3.15

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 49).

Unless otherwise specified, the parameters given in Table 52 are derived from tests

performed under ambient temperature and VDD supply voltage conditions summarized in

Table 10.

Figure 45.

Recommended NRST pin protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 52. Otherwise the reset will not be taken into account by the device.

ai14131

10%

90%

50%

tr(IO)out

OUTPUT

EXT ERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)

10%

50%

90%

when loaded by 50pF

tr(IO)out

Table 52.

NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST)

(1)

Guaranteed by design, not tested in production.

NRST Input low level voltage

–0.5

0.8

VIH(NRST)

(1)

NRST Input high level voltage

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

RPU

Weak pull-up equivalent resistor(2)

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum

(~10% order)

VIN = VSS

VF(NRST)

(1)

NRST Input filtered pulse

100

VNF(NRST)

(1)

NRST Input not filtered pulse

300

ai14132d

STM32F10xxx

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 µF

External

reset circuit(1)

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