전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

STM8S103F2P3TR 데이터시트(PDF) 83 Page - STMicroelectronics

부품명 STM8S103F2P3TR
상세설명  Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
PDF  113 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8S103F2P3TR 데이터시트(HTML) 83 Page - STMicroelectronics

Back Button STM8S103F2P3TR Datasheet HTML 79Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 80Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 81Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 82Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 83Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 84Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 85Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 86Page - STMicroelectronics STM8S103F2P3TR Datasheet HTML 87Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 83 / 113 page
background image
Unit
Fast mode I
2C(1)
Standard mode I
2C
Parameter
Symbol
Max
(2)
Min
(2)
Max
(2)
Min
(2)
0.6
4.0
STOP condition setup time
tsu(STO)
μs
1.3
4.7
STOP to START condition time
(bus free)
tw(STO:STA)
pF
400
400
Capacitive load for each bus line
Cb
(1) f
MASTER, must be at least 8 MHz to achieve max fast I
2C speed (400kHz)
(2) Data based on standard I2C protocol requirement, not tested in production
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 42: Typical application with I
2C bus and timing diagram
tf(SDA)
tr(SDA)
tsu(SDA)
th(SDA)
tf(SCL)
tr(SCL)
tw(SCLL)
tw(SCLH)
th(STA)
tsu(STO)
tsu(STA)
tw(STO:STA)
SDA
SCL
4.7k
Ω
SDA
SCL
100
Ω
100
Ω
4.7k
Ω
I2C bus
START
START
STOP
REPEATED
START
STM8S
V
DD
V
DD
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10-bit ADC characteristics
10.3.10
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
83/113
DocID15441 Rev 6
Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com