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ASM7306C 데이터시트(PDF) 3 Page - Aplus Intergrated Circuits |
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ASM7306C 데이터시트(HTML) 3 Page - Aplus Intergrated Circuits |
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3 / 7 page ![]() ASM7306C Rev 1.0 2002/09/22 2 FIGURE 1.1 : Block Diagram of ASM7306C COUT OSC VDD/GND ROM 1 PC[11:0] ROM Latch Instruction Latch Instruction Decoder 0 PCH(8) PCL(4) PCLATCH(8) DPR3,2,1 Program DLATCH(10) Clock Generator Power on Reset Test select P1,P2,P3,P4 enter test mode Timer0(9) Reset Chip Stack(12) Data Bus[3:0] Instruction Bus [9:0] ROM_ADDR[17:0] ROM_Data[9:0] Data Bus[3:0] Control Signal ADDR[17:0] =00000b (ADDR[17:12]) PRASL(4) weak or strong pull-low for PRA, (Data) Instruction Bus [9:0] ( Voice synthesizer ) One-Channel SRAM (64 x 4) 40h-5Fh (2-Level) ALU(4) Register(4) Accumlator(4) Immediate(4) DPR[17:0] RESET pin Reset Chip 00h-1Fh PRA(4) PRB(2) PRB, PRC COUT |
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