AD7682BCPZ datasheet(31/32 Pages) AD

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Data Sheet

AD7682/AD7689

Rev. D | Page 31 of 32

APPLICATION HINTS

LAYOUT

The printed circuit board (PCB) that houses the AD7682/AD7689

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. The pinout of

the AD7682/AD7689, with all its analog signals on the left side

and all its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these

couple noise onto the die unless a ground plane under the

AD7682/AD7689 is used as a shield. Fast switching signals,

such as CNV or clocks, should not run near analog signal

paths. Avoid crossover of digital and analog signals.

At least one ground plane should be used. It can be common or

split between the digital and analog sections. In the latter case,

the planes should be joined underneath the AD7682/AD7689.

The AD7682/AD7689voltage reference input REF has a

dynamic input impedance and should be decoupled with

minimal parasitic inductances. This is done by placing the

reference decoupling ceramic capacitor close to, ideally right up

against, the REF and GND pins and connecting them with wide,

low impedance traces.

Finally, the power supplies VDD and VIO of the AD7682/

AD7689 should be decoupled with ceramic capacitors, typically

100 nF, placed close to the AD7682/AD7689, and connected

using short, wide traces to provide low impedance paths and to

reduce the effect of glitches on the power supply lines.

EVALUATING AD7682/AD7689 PERFORMANCE

Other recommended layouts for the AD7682/AD7689 are

outlined in the documentation of the evaluation board for the

AD7682/AD7689 (EVAL-AD7682EDZ/EVAL-AD7689EDZ).

The evaluation board package includes a fully assembled and

tested evaluation board, documentation, and software for

controlling the board from a PC via the converter and evaluation

development data capture board, EVAL-CED1Z.

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