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AS3517H-ECTP 데이터시트(PDF) 27 Page - ams AG

부품명 AS3517H-ECTP
상세설명  Stereo Audio Codec with enhanced System Power Management
PDF  94 Pages
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제조업체  AMSCO [ams AG]
홈페이지  http://www.ams.com
Logo AMSCO - ams AG

AS3517H-ECTP 데이터시트(HTML) 27 Page - ams AG

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AS3517 V17
Data Sheet, Confidential
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Figure 11 I2S Timing
Table 22 Audio Converter Parameter
Symbol
Parameter
Min
Typ
Max
Unit
Note
tSCLK
SCLK Cycle Time
160
ns
tSCLKH
SCLK Pulse Width High
80
ns
tSCLKL
SCLK Pulse Width Low
80
ns
TLRSU
LRCLK Setup Time before
SCLK rising edge
80
ns
TLRHD
LRCLK Hold Time after SCLK
rising edge
80
ns
tSDSU
SDI setup time before SCLK
rising edge
25
ns
tSDHD
SDI hold time after SCLK
rising edge
25
ns
tSDOD
SDO Delay from SCLK falling
edge
25
ns
tJITTER
Jitter of LRCLK
-20
20
ns
internal PLL generates
MCLK from LRCLK
I2S Direct mode
TSCD
SCLK delay after MCLK
rising edge
0.5
1.5
ns
TLRD
LRLCK delay after SCLK
rising edge
0.5
1.5
ns
tSDSU
SDI setup time before SCLK
rising edge
5
ns
tSDHD
SDI hold time after SCLK
rising edge
5
ns
tSDOD
SDO Delay from SCLK falling
edge
15
ns
VI2SH
SCLK, LRCLK, SDI, MCLK
High Input Level
1.02
V
DVDD/2*0.7
VI2SL
SCLK, LRCLK, SDI, MCLK
Low Input Level
0.42
V
DVDD/2*0.3
VSDOH
SDO High Output Level
2.6
V
at 2mA
VSDOL
SDO Low Output Level
0.3
V
at 2mA
VI2SOH
SCLK, LRCLK, High Output
Level
2.6
V
at 8mA master mode only
VI2SOL
SCLK, LRCLK, Low Output
Level
0.3
V
at 8mA master mode only
BVDD=3.3V, TA=25°C, Slave Mode, fS=48kHz, MCLK = 256*fS, unless otherwise specified
Revision 1v3
26
- 93



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