AS3543 datasheet(84/92 Pages) AMSCO

84 / 92 page

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Revision 1.11

83 - 91

AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

HP_OVC

(level)

Headphone over-current interrupt setting

0: disable

1: enable

The interrupt must not be enabled if the headphone block is

disabled

Headphone over-current interrupt reading

0: no over-current detected

1: headphone over-current detected, headphone amplifier was

shut down. The current thresholds are 150mA at HPR / HPL

pin or 300mA at HPCM pin.

I2S_status

0: no LRCK on I2S interface detected

1: LRCK on I2S interface present

I2S_IRQ

I2S input status change interrupt setting

0: disable

1: enable

I2S_changed

(status change)

I2S input status change interrupt reading

0: I2S input status not changed

1: I2S input status changed, check I2S_status

VOXM_IRQ

Enables interrupt which is invoked by reaching a voltage

threshold at the MIC input (voice activation)

0: disable

1: enable

This bit is set when a voltage threshold of 5mVRMS (unfiltered)

at the MIC has been reached (voice activation)

MIC_CON

(level)

Microphone connect detection interrupt setting

0: disable

1: enable

Microphone connect detection interrupt reading

0: no microphone connected to MIC input

1: microphone connected at MIC input.

This interrupt is only invoked when the microphone stage is

powered down. The IRQ will be released after enabling the

microphone stage.

Detecting a microphone during operation has to be done by

measuring the supply current

HPH_CON

(level)

Headphone connect detection interrupt setting

0: disable

1: enable

Headphone connect detection interrupt reading

0: no headphone connected

1: headphone connected

This interrupt is only invoked when the headphone stage is

powered down. The IRQ will be released after enabling the

headphone stage.

Detecting a headphone during operation is not possible.

Table 85. Fourth Interrupt Register

Name

Base

Default

IRQENRD_3

2-wire serial

00h

Offset: 26h

Fourth Interrupt Register

Please be aware that writing to this register will enable/disable the

corresponding interrupts, while reading gets the actual interrupt status and

will clear the register at the same time. It is not possible to read back the

interrupt enable/disable settings. This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

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