AS8515 datasheet(44/65 Pages) AMSCO

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AS8515

Datasheet - 4-W i re SPI Interf ace

9 4-Wire SPI Interface

The SPI interface can also be used as interface between the AS8515 and an external micro-controller to configure the device and access the

status information. Micro-controller begins communication with the SPI configured as a slave. The SPI protocol is very simple and the length of

each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bits, 5 address/

configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done

on each start of the SPI transaction. During the transaction SPI clock polarity will be fixed to the settings done. On the CS falling edge the values

on SCLK signal decide setting of the active SPI clock edge for data transfer (see Table 46).

9.1 SPI Timing Parameters

Table 46. CS and SCLK

1. Pin CST is used to program top device and pin CSB is used to program bottom device.

SCLK

Description

FALL

LOW

Serial data transferred on rising edge of SPI clock.

Sampled at falling edge of SPI clock.

FALL

HIGH

Serial data transferred on falling edge of SPI clock.

Sampled at rising edge of SPI clock.

ANY

Serial data transfer edge is unchanged.

Table 47. 4-Wire Serial Port Interface

Symbol

Parameter

Conditions

Min

Typ

Max

Units

General

BRSPI

Bit rate

250

Kbps

TSCLKH

Clock high time

µs

TSCLKL

Clock low time

µs

Write Timing

tDIS

Data in setup time

tDIH

Data in hold time

TCSH

CS hold time

Read Timing

tDOD

Data out delay

tDOHZ

Data out to high impedance delay

Time for the SPI to release the SDO bus

Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)

tCPS

Clock setup time

(CLK polarity)

Setup time of SCLK with respect to

CS falling edge

tCPHD

Clock hold time

(CLK polarity)

Hold time of SCLK with respect to

CS falling edge

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