I2CSTAT datasheet(66/210 Pages) MICROCHIP

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dsPIC30F2011/2012/3012/3013

DS70139G-page 66

8.1

Interrupt Priority

The user-assignable interrupt priority bits (IP<2:0>) for

each individual interrupt source are located in the

LS 3 bits of each nibble within the IPCx register(s). Bit

3 of each nibble is not used and is read as a ‘0’. These

bits define the priority level assigned to a particular

interrupt by the user.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 8-1 lists the interrupt numbers and interrupt

sources

for

the

dsPIC30F2011/2012/3012/3013

devices and their associated vector numbers.

The ability for the user to assign every interrupt to one

of seven priority levels means that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD

(Low Voltage Detect) can be given a priority of 7. The

INT0 (External Interrupt 0) may be assigned to priority

level 1, thus giving it a very low effective priority.

TABLE 8-1:

INTERRUPT VECTOR TABLE

Note:

The user-assignable priority levels start at

0 as the lowest priority and level 7 as the

highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

Interrupt

Number

Vector

Number

Interrupt Source

Highest Natural Order Priority

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

T1 – Timer 1

IC2 – Input Capture 2

OC2 – Output Compare 2

T2 – Timer2

T3 – Timer3

816

SPI1

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC – ADC Convert Done

NVM – NVM Write Complete

SI2C – I2C™ Slave Interrupt

MI2C – I2C Master Interrupt

Input Change Interrupt

INT1 – External Interrupt 1

17-22

25-30

Reserved

INT2 – External Interrupt 2

U2RX(1) – UART2 Receiver

U2TX(1) – UART2 Transmitter

26-41

34-49

Reserved

LVD – Low-Voltage Detect

43-53

51-61

Reserved

Lowest Natural Order Priority

Note 1:

Only the dsPIC30F3013 has UART2 and

the U2RX, U2TX interrupts. These

locations are reserved for the

dsPIC30F2011/2012/3012.

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