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LTC1289BCSW 데이터시트(PDF) 14 Page - Linear Technology

부품명 LTC1289BCSW
상세설명  3 Volt Single Chip 12-Bit Data Acquisition System
PDF  28 Pages
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제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTC1289BCSW 데이터시트(HTML) 14 Page - Linear Technology

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14
LTC1289
1289fb
S
APPLICATI
I FOR ATIO
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1289 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1289 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1289 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
Figure 4. CS Low During Conversion
Figure 3. CS High During Conversion
Low CS Recognized Internally
High CS Recognized Internally
CS
ACLK
DOUT
Hi-Z
VALID OUTPUT
LTC1289 AI08
CS
ACLK
DOUT
Hi-Z
VALID OUTPUT
LTC1289 AI08a
DON'T CARE
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SHIFT RESULT OUT
AND NEW ADDRESS IN
SCLK
CS
DOUT
DIN
tSMPL
SAMPLE ANALOG
INPUT
SHIFT
MUX ADDRESS
IN
LTC1289 AIF03
48 TO 52
ACLK CYC
DON'T CARE
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8B7
B6
B5
B4
B3B2
B1B0
SHIFT RESULT OUT
AND NEW ADDRESS IN
SCLK
CS
DOUT
DIN
tSMPL
SAMPLE ANALOG
INPUT
SHIFT
MUX ADDRESS
IN
LTC1289 AIF04
48 TO 52
ACLK CYC
SCLK MUST
REMAIN LOW



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