CS4294 datasheet(27/42 Pages) CIRRUS

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CS4294

DS326PP4

6.1.25 GPIO Pin Configuration (Index 4Ch)

GC[9:0]

GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input

Default

03FFh

After a cold reset, power up, or extended codec register reset (see Extended Codec ID (Index 3Ch))

all GPIO pins are configured as inputs.

6.1.26 GPIO Pin Polarity/Type Configuration (Index 4Eh)

GP[9:0]

GPIO Pin Configuration. The definition of GP[8:3] changes based on the pin defined as an input or an

output by GC[8:3] of GPIO Pin Configuration (Index 4Ch).

Default

FFFFh

When the GPIO pin is defined as an input, its status is reported in the GPIO Pin Status (Index 54h)

6.1.27 GPIO Pin Sticky (Index 50h)

GS[8:3]

GPIO Pin Sticky. If set, the GPIO pin input is latched.

Default

0000h

If a GPIO is defined as “sticky” the input requires a transition of the GPIO input pin to set the corre-

sponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When “sticky” is set the corre-

sponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge

of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to

low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the “sticky” input.

D15

D14

D13

D12

D11

D10

res

GC8

GC7

GC6

GC5

GC4

GC3

res

D15

D14

D13

D12

D11

D10

res

GP8

GP7

GP6

GP5

GP4

GP3

res

GCx

GPx

Function

Output

CMOS drive

Output

Open drain

Input

Active Low

Input

Active High (default)

Table 7. GPIO Input/Output Configuration

D15

D14

D13

D12

D11

D10

GS8

GS7

GS6

GS5

GS4

GS3

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