CS42L50 datasheet(14/48 Pages) CIRRUS

14 / 48 page

CS42L50

DS544PP1

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)

Note: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-100

KHz

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

µs

Clock Low time

tlow

4.7

µs

Clock High Time

thigh

4.0

µs

Setup Time for Repeated Start Condition

tsust

4.7

µs

SDA Hold Time from SCL Falling

(Note 17)

thdd

µs

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL

trc

-25

Fall Time of SCL

tfc

-25

Rise Time of SDA

trd

-1

µs

Fall Time of SDA

tfd

-300

Setup Time for Stop Condition

tsusp

4.7

µs

buf

hdst

low

t r

t f

hdd

high

t sud

t sust

t susp

Stop

S ta rt

Sta rt

Stop

R e pe ate d

SD A

SC L

irs

RS T

Figure 3. Control Port Timing - I2Câ

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