CS4340

DS297PP3

13

3.

PIN DESCRIPTION

RST

1

Reset (

Input) - The device enters a low power mode and all internal state machines are reset to

the default settings when low. RST should be held low during power-up until the power supply,

master and left/right clocks are stable.

SDATA

2

Serial Audio Data (

Input) - Two’s complement MSB-first serial data is input on this pin. The

data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right

clock. The required relationship between the Left/Right clock, serial clock and serial data is

defined by the DIF1-0 pins. The options are detailed in Figures 16-19.

SCLK

3

Serial Clock (

Input) - Clocks the individual bits of the serial data into the SDATA pin. The

required relationship between the Left/Right clock, serial clock and serial data is defined by the

DIF1-0 pins. The options are detailed in Figures 16-19.

The CS4340 supports both internal and external serial clock generation modes. Internal SCLK

mode is used to gain access to extra de-emphasis modes.

Internal Serial Clock Mode - In the Internal Serial Clock Mode, the serial clock is internally

derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency

ratio is either 32, 48, or 64 depending upon the DIF1-0 pins as shown in Figures 16-19. Opera-

tion in this mode is identical to operation with an external serial clock synchronized with LRCK.

External Serial Clock Mode - The CS4340 will enter the External Serial Clock Mode whenever

16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period.

The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on

the SCLK pin for 2 consecutive periods of LRCK.

15

2

14

3

13

4

16

1

11

6

10

7

9

8

12

5

Reset

RST

MUTEC

Mute Control

Serial Data

SDATA

AOUTL

Left Analog Output

Serial Clock / De-emphasis SCLK/DEM1

VA

Analog Power

Left/Right Clock

LRCK

AGND

Analog Ground

Master Clock

MCLK

AOUTR

Right Analog Output

Digital Interface Format

DIF1

REF_GND Reference Ground

Digital Interface Format

DIF0

VQ

Quiescent Voltage

De-emphasis

DEM0

FILT+

Positive Voltage Reference