CS4340

14

DS297PP3

DEM1 and DEM0

3 & 8 De-emphasis Control (

Input) - Implementation of the standard 15

µs/50µs digital de-emphasis

filter response, Figure 20, requires reconfiguration of the digital filter to maintain the proper filter

response for 32, 44.1 or 48 kHz sample rates. When using Internal Serial Clock Mode, as

described above, Pin 3 is available for de-emphasis control, DEM1, and all de-emphasis filters

are available, Table 3. When using External Serial Clock Mode, as described above, Pin 3 is

not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is available,

Table 4. NOTE: De-emphasis is not available in High-Rate Mode.

LRCK

4

Left/Right Clock (

Input) - The Left/Right clock determines which channel is currently being

input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at

the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output

from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period

difference. The required relationship between the Left/Right clock, serial clock and serial data is

defined by the DIF1-0 pins. The options are detailed in Figures 16-19.

MCLK

5

Master Clock (

Input) - The master clock frequency must be either 256x, 384x or 512x the input

sample rate in Base Rate Mode (BRM) and either 128x or 192x the input sample rate in High

Rate Mode (HRM). Table 3 illustrates several standard audio sample rates and the required

master clock frequencies.

DEM1

DEMO

DESCRIPTION

00

Disabled

01

44.1kHz

10

48kHz

11

32kHz

Table 1. Internal Serial Clock Mode

DEMO

DESCRIPTION

0

Disabled

1

44.1kHz

Table 2. External Serial Clock Mode

Sample

Rate

(kHz)

MCLK (MHz)

HRM

BRM

128x

192x

256x

384x

512x

32

4.0960

6.1440

8.1920

12.2880

16.3840

44.1

5.6448

8.4672

11.2896

16.9344

22.5792

48

6.1440

9.2160

12.2880

18.4320

24.5760

64

8.1920

12.2880

-

-

-

88.2

11.2896

16.9344

-

-

-

96

12.2880

18.4320

-

-

-

Table 3. Common Master Clock Frequencies