CS49300 datasheet(68/86 Pages) CIRRUS

68 / 86 page

CS49300 Family DSP

DS339PP4

is presented most significant bit first. It should be

noted that in the multichannel modes the SCLK

rate must be greater than the number of bits per

channel multiplied by the number of channels. In

the example SCLK must be greater than M * 6.

Because each of the ports is fully configurable

(SCLK polarity, LRCLK polarity, Word Width,

SCLK Rate) not all modes have been presented.

10.2. Digital Audio Input Port

The digital audio input port, or DAI, is used for

both compressed and PCM digital audio data input.

In addition this port supports a special clocking

mode in which a clock can be input to directly drive

the internal 33 bit counter. Table 13, “Digital

Audio Input Port,” on page 68 shows the pin

names, mnemonics and pin numbers associated

with the DAI.

The DAI is fully configurable including support for

I2S, left justified and multichannel formats. In

addition the DAI can be programmed for slave

clocks, where LRCLKN1 and SCLKN1 are inputs,

or master clocks, where LRCLKN1 and SCLKN1

are outputs. In order for clocks to be master, the

internal PLL must be used.

STCCLK2 can also be programmed to drive the

internal 33 bit counter. This counter would

typically be driven by a 90kHz clock. The internal

LRCK

SC L K

SD AT A

MS B

LS B

Le ft

R ig ht

MS B

LS B

Figure 43. I2S Format

L RCK

SC L K

SD AT A

MS B

LS B

Le ft

R ig ht

MS B

LS B

MS B

Figure 44. Left Justified Format (Rising Edge Valid SCLK)

LR C L K

SC L K

SD ATA

MS B

L S B

M C lo ck s

P e r C hannel

MS B

L S B

M Clock s

P er Channel

M C lo ck s

P e r C h annel

MS B

L S B

M C lo c ks

P e r C hann el

MS B

L S B

M C lo ck s

P e r C hannel

MS B

L S B

M Clo ck s

P er Ch annel

MS B

L SB

MS B

Figure 45. Multichannel Format

Pin Name

Pin Description

Pin Number

SDATAN1

STCCLK2

Serial Data In

Secondary STC clock

SCLKN1

Serial Bit Clock

LRCLKN1

Frame Clock

Table 13. Digital Audio Input Port

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