CS49310 datasheet(18/86 Pages) CIRRUS

18 / 86 page

CS49300 Family DSP

DS339PP4

1.12. Switching Characteristics — CMPDAT, CMPCLK

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

1.13. Switching Characteristics — Parallel Data Input

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows:

External CLKIN Mode:

DCLK == CLKIN/4 before and during boot

DCLK == CLKIN after boot

Internal Clock Mode:

DCLK == 10MHz before and during boot, i.e. DCLK == 100ns

DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

Parameter

Symbol

Min

Max

Unit

Serial compressed data clock CMPCLK period

Tcmpclk

-27

MHz

CMPDAT setup before CMPCLK high

Tcmpsu

CMPDAT hold after CMPCLK high

Tcmphld

Parameter

Symbol

Min

Max

Unit

CMPCLK Period

Tcmpclk

4*DCLK + 10

DATA[7:0] setup before CMPCLK high

Tcmpsu

DATA[7:0] hold after CMPCLK high

Tcmphld

CM P CL K

Tcm psu

Tcm pclk

CM PDAT

Tcm phld

Figure 10. Serial Compressed Data Timing

CM P C L K

Tcm psu

Tcm pclk

D A T A [7:0 ]

Tcm phld

Figure 11. Parallel Data Timing (when not in a parallel control mode)

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