CS494502 datasheet(3/100 Pages) CIRRUS

3 / 100 page

2.1 DSPAB ............................................................................................................................ 36

2.2 DSPC ............................................................................................................................... 36

3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 37

3.1 Multiplexed Pins ..............................................................................................................37

3.2 Termination Requirements .............................................................................................. 37

3.3 Phase Locked Loop Filter ................................................................................................ 37

4. POWER

.............................................................................................................................. 38

4.1 Decoupling ....................................................................................................................... 38

4.2 Analog Power Conditioning ............................................................................................. 38

4.3 Ground ............................................................................................................................. 38

4.4 Pads ................................................................................................................................ 38

5. CLOCKING ............................................................................................................................. 42

6. CONTROL .............................................................................................................................. 42

6.1 Serial Communication ..................................................................................................... 42

6.1.1 SPI Communication for DSPAB .......................................................................... 42

6.1.2 SPI Communication for DSPC ............................................................................ 46

6.1.3 FINTREQ Behavior: A Special Case .................................................................. 49

6.2 Parallel Host Communication for DSPAB ........................................................................ 51

6.2.5 Intel Parallel Host Communication Mode for DSPAB ......................................... 51

6.2.6 Motorola Parallel Communication Mode for DSPAB ........................................... 54

6.2.7 Procedures for Parallel Host Mode Communication for DSPAB ......................... 56

6.3 Parallel Host Communication for DSPC .......................................................................... 58

6.3.5 Intel Parallel Host Communication Mode for DSPC ............................................ 60

6.3.6 Motorola Parallel Host Communication Mode for DSPC .................................... 64

6.3.7 Procedures for Parallel Host Mode Communication for DSPC ........................... 68

7. EXTERNAL MEMORY ............................................................................................................ 70

7.1 Configuring SRAM Timing Parameters ........................................................................... 71

8. BOOT PROCEDURE .............................................................................................................. 72

8.1 Host Controlled Master Boot ........................................................................................... 72

8.2 Host Boot Via DSPC ........................................................................................................ 75

9. SOFT RESETTING THE CS49400 ......................................................................................... 77

9.1 Host Controlled Master Soft Reset .................................................................................. 77

10. HARDWARE CONFIGURATION ......................................................................................... 79

11. DIGITAL INPUT AND OUTPUT DATA FORMATS .............................................................. 79

11.1 Digital Audio Formats .................................................................................................... 79

11.1.1 I2S ..................................................................................................................... 79

11.1.2 Left Justified ...................................................................................................... 79

11.2 Digital Audio Input Port .................................................................................................. 79

11.3 Compressed Data Input Port ......................................................................................... 80

11.4 Input Data Hardware Configuration for CDI and DAI on DSPAB ................................. 80

11.4.1

Input Configuration Considerations ................................................................ 81

11.5 Serial Audio Input .......................................................................................................... 82

11.6 Digital Audio Output Port ............................................................................................... 82

11.6.1 S/PDIF Outputs ................................................................................................. 83

11.7 Output Data Hardware Configuration ............................................................................ 84

11.8 Creating Hardware Configuration Messages ................................................................. 85

12.0 PIN DESCRIPTION ............................................................................................................. 87

12.1 144-Pin LQFP Package Pin Layout ............................................................................... 87

12.2 100-Pin LQFP Package Pin Layout ............................................................................... 88

12.3 Pin Definitions ................................................................................................................ 89

13. ORDERING INFORMATION ................................................................................................ 99

14. PACKAGE DIMENSIONS .................................................................................................. 100

14.1 144-Pin LQFP Package ............................................................................................... 100

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