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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DS80C400 데이터시트(PDF) 5 Page - Dallas Semiconductor |
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DS80C400 데이터시트(HTML) 5 Page - Dallas Semiconductor |
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5 / 97 page  DS80C400 Network Microcontroller 5 of 97 PARAMETER SYMBOL MIN MAX UNITS STRETCH VALUES CST (MD2:0) tCLCL - 5 CST = 0 2tCLCL - 5 1 £ CST £ 3 Data Float After RD (P3.7 or PSEN) High tRHDZ 6tCLCL - 5 ns 4 £ CST £ 7 2tCLCL + tCLCH - 19 CST = 0 (4 x CST + 1) tCLCL - 19 1 £ CST £ 3 ALE Low to Valid Data In tLLDV (4 x CST + 5) tCLCL - 19 ns 4 £ CST £ 7 3tCLCL - 19 CST = 0 (4 x CST + 2)tCLCL - 19 1 £ CST £ 3 Port 0 Address to Valid Data In tAVDV0 (4 x CST + 10)tCLCL - 19 ns 4 £ CST £ 7 3tCLCL + tCLCH - 19 CST = 0 (4 x CST + 2)tCLCL + tCLCH - 19 1 £ CST £ 3 Port 2, 4, 6 Address, Port 4 CE, or Port 5 PCE to Valid Data In tAVDV2 (4 x CST + 10)tCLCL + tCLCH - 20 ns 4 £ CST £ 7 tCLCH - 3 tCLCH + 6 CST = 0 tCLCL - 3 tCLCL + 6 1 £ CST £ 3 ALE Low to ( RD or PSEN) or WR Low tLLWL 5tCLCL - 3 5tCLCL + 6 ns 4 £ CST £ 7 tCLCL - 5 CST = 0 2tCLCL - 6 1 £ CST £ 3 Port 0 Address to ( RD or PSEN) or WR Low tAVWL0 10tCLCL - 6 ns 4 £ CST £ 7 tCLCL + tCLCH - 5 CST = 0 2tCLCL + tCLCH - 5 1 £ CST £ 3 Port 2, 4 Address, Port 4 CE, Port 5 PCE, to ( RD or PSEN) or WR Low tAVWL2 10tCLCL + tCLCH - 5 ns 4 £ CST £ 7 Data Valid to WR Transition tQVWX 0 ns tCLCL - 4 CST = 0 2CLCL - 7 1 £ CST £ 3 Data Hold After WR High tWHQX 6tCLCL - 7 ns 4 £ CST £ 7 RD Low to Address Float tRLAZ (Note 2) 0 £ CST £ 7 0 7 CST = 0 tCLCL - 3 tCLCL + 4 1 £ CST £ 3 ( RD or PSEN) or WR High to ALE tWHLH 5tCLCL - 3 5tCLCL + 4 ns 4 £ CST £ 7 tCHCL -5 tCHCL + 13 CST = 0 tCLCL + tCHCL - 5 tCLCL + tCHCL + 13 1 £ CST £ 3 ( RD or PSEN) or WR High to Port 4 CE or Port 5 PCE High tWHLH2 5tCLCL + tCHCL - 5 5tCLCL + tCHCL + 13 ns 4 £ CST £ 7 Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory. Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted. Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL , tCLCH , tCHCL are time periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table. Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 ( CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7). Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for determing absolute signal timing with respect to the external clock. |
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