AD7653 datasheet(5/24 Pages) AD

5 / 24 page

Data Sheet

AD7625

Rev. A | Page 5 of 24

TIMING SPECIFICATIONS

VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Time Between Conversions1

CYC

166

10,000

Acquisition Time

ACQ

CNV± High Time

CNVH

CNV± to D± (MSB) Delay

MSB

145

CNV± to Last CLK± (LSB) Delay

CLKL

110

CLK± Period2

CLK

CYC − tMSB + tCLK)/n

3.33

CLK± Frequency

CLK

250

300

MHz

CLK± to DCO± Delay (Echoed-Clock Mode)

DCO

DCO± to D± Delay (Echoed-Clock Mode)

CLK± to D± Delay

CLKD

1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of t

CYC, the subsequent conversion result is invalid.

2 For the minimum CLK period, the window available to read data is t

CYC − tMSB + tCLK. Divide this time by the number of bits (n) that are read. In echoed-clock interface

mode, n = 16; in self-clocked interface mode, n = 18.

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